The Time-Varying Nature Of Cache Utilization A Case Study On The Mantevo And Apex Benchmarks

Computer architects have been utilizing cache hierarchies to improve performance by minimizing latency of main memory accesses via caching frequently used data closer to the core. The majority of prior research focuses on measuring cache hit rates and data movement for the entire run of an application. We present cache performance metrics as they vary with the execution progression of the application, and show how these metrics can provide improved insight about application behavior. In this work, we present runtime cache utilization, as well as, conventional performance metrics that illustrate a holistic understanding of cache behavior. We built and incorporated a memory simulator into the Structural Simulation Toolkit (SST). We measure and analyze the performance for several scientific mini-applications from the APEX and Mantevo suites. This characterization can help identify the critical program points in benchmarks that may reduce the overall simulation time while testing new designs. Moreover, this introductory work enables us to quantify cache behavior for our work that proposes an on-chip memory with dynamic adaptive cache line size that is expected to reduce power consumption.