A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction.

Ting-Kuei Kuan,Shen-Iuan Liu

2015 Symposium on VLSI Circuits (VLSI Circuits)（2015）

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关键词
digital bang-bang phase locked loop,automatic loop gain control,loop latency reduction technique,jitter performance,CMOS integrated circuit,size 40 nm,power 3.8 mW,voltage 1.1 V,frequency 3.96 GHz
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