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A design of 13dBm IIP3 DVB-S.2 RF receiver with auto calibration technique

Asia Pacific Microwave Conference-Proceedings(2008)

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摘要
In this paper a full integrated CMOS single chip DCR DBS is presented. The receiver covered 0.95 GHz to 2.15 GHz broadband frequency. It contains an automatically gain controlled RF front-end including LNA, RFVGA, WBD/RSSI and proposed automatically fine controlled VCO band a role in good phase noise optimization with Fractional-N PLL. A fully programmable channel select filter effectively eliminates out of channel jammers. The proposed receiver shows a remarkable linearity performance 13 dBm of IIP3 at the minimum gain and wide dynamic range is over 80 dB. The high linearity, good phase noise and wide dynamic gain performance at low power consumption make it well suitable to the DVB-S2 application.
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关键词
phase locked loops,chip,automatic gain control,front end,vco,radio frequency,lna,satellites,direct conversion receiver,gain,digital video broadcasting,cmos integrated circuits,phase noise
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