A 32kB 2R/1W L1 data cache in 45nm SOI technology for the POWER7TM processor

Pille, J.,Wendel, D., Wagner, O.,Sautter, R.

Solid-State Circuits Conference Digest of Technical Papers（2010）

引用 18|浏览3

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关键词

CMOS integrated circuits,cache storage,microprocessor chips,random-access storage,silicon-on-insulator,6T-SRAM cell,CMOS SOI technology,POWER7 microprocessor,SRAM cell stability,array-specific power supply,data cache,logic voltage level,read/write collision,write-over-read priority

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