A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Jan, C.-H.,Agostinelli, M., Buehler, M.,Chen, Z.-P.,S J Choi,G Curello,H Deshpande,S Gannavaram,W Hafez,U Jalan, Min Kang,P Kolar,K Komeyli, B Landau, Adam Lake,Noel D Lazo, Sang Hyun Lee,T Leo,J Lin,Nick Lindert,Shengqian Ma, L Mcgill,C J Meining, A Paliwal,Jaesung Park,K Phoa, I R C Post, N K Pradhan, M B Prince,A Rahman,J Rizk,Lee David Rockford,Gavin L Sacks,Anthony Schmitz,Hiroko Tashiro, Chienchung Tsai,P Vandervoorn, J Xu,L Yang,J Y Yeh,Jim Yip,Kai Zhang,Y Zhang,P Bai

Electron Devices Meeting（2009）

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关键词

SRAM chips,capacitors,inductors,interconnections,mixed analogue-digital integrated circuits,nanotechnology,optimisation,passive networks,resistors,system-on-chip,transistors,I-O devices,RF-analog passive elements,SRAM,SoC platform technology,capacitors,deep-nwell noise isolation,embedded memories,embedded memory,high density product applications,high performance product applications,high quality passives,high-k-metal gate transistors,inductors,interconnects,mix-and-match transistors,noise mitigation options,resistors,secure OTP fuses,size 32 nm,ultralow power applications

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