Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects
SOI-3D-Subthreshold Microelectronics Technology Unified Conference（2014）
关键词
copper,integrated circuit interconnections,integrated circuit metallisation,integrated memory circuits,low-temperature techniques,three-dimensional integrated circuits,wafer bonding,ITRS roadmap,integrated interconnect system,intervia strategy,intravia strategy,low-temperature oxide wafer bonding,multistacked memory wafer,ultrafine-dimension TSV metallization,ultrafine-dimension copper through-silicon via interconnect,via-last strategy,via-middle strategy,3D,DRAM,TSV,oxide bonding,wafer stacking,
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