A variation tolerant architecture for ultra low power multi-processor cluster

Bortolotti, D.,Rossi, D.,Bartolini, A.,Benini, L.

Power and Timing Modeling, Optimization and Simulation（2013）

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flip-flops,integrated circuit reliability,low-power electronics,multiprocessing systems,ULP devices,datapath dynamically-adapting latency,detrimental effect,embedded system reliability,energy efficiency,environmental temperature variation,flip-flops,hold time,process variation,reliability gain,setup time sensitivity,supply voltage,ultralow-power multiprocessor cluster,variation tolerant architecture,

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