ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process

Alexandre Dray,Nicolas Guitard,Pascal Fonteneau,Dominique Golanski,C Fenouilletberanger, Helene Beckrich,Radhakrishnan Sithanandam,T Benoist,C Legrand,Ph Galy

Electrical Overstress/Electrostatic Discharge Symposium（2012）

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摘要

This paper presents an innovative way to design competitive ESD protection networks in advanced FDSOI CMOS technology thanks to Hybrid Bulk co-integration. An optimal placement of elementary ESD devices is discussed and their ESD performances are compared. The advantage of the co-integration is also demonstrated on an ESD network design development.

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electrostatic discharge,cmos integrated circuits,silicon on insulator

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