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FinFET resistance mitigation through design and process optimization

Cindy Wang,Josephine Chang,Chunghsun Lin,Arvind Kumar,Andreas Gehring,Jin Cho,Amlan Majumdar, Andreas Bryant,Z Ren,K Chan,T Kanarsky,Xinlin Wang,O Dokumaci,Michael A Guillorn,Marwan H Khater,Qingyun Yang, Xi Li,Munir D Naeem,Judson R Holt, Yongsik Moon, J King,John R Yates,Ying Zhang,Daegyu Park,Christine Ouyang,Wilfried Haensch

Hsinchu（2009）

Cited 9|Views60
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Key words
mosfet,circuit cad,finfet,design optimization,parasitic resistance,process optimization,resistance mitigation,size 22 nm,size 45 nm,process design,silicon,electrostatics,logic gates,doping,hafnium,3 dimensional,parasitic capacitance,contact resistance,degradation,immune system
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