32Nm General Purpose Bulk CMOS Technology for High Performance Applications at Low Voltage

F. Arnaud, J. Liu,Y. M. Lee,K. Y. Lim,S. Kohler,J. Chen,B. K. Moon,C. W. Lai, M. Lipinski, L. Sang,F. Guarin, C. Hobbs,P. Ferreira,K. Ohuchi, J. Li,H. Zhuang, P. Mora,Q. Zhang,D. R. Nair, D. H. Lee,K. K. Chan, S. Satadru,S. Yang, J. Koshy, W. Hayter,M. Zaleski,D. V. Coolbaugh, H. W. Kirn, Y. C. Ee,J. Sudijono,A. Thean,M. Sherony,S. Samavedam,M. Khare,C. Goldberg,A. Steegen

2008 IEEE International Electron Devices Meeting（2008）

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Key words

1/f noise,CMOS digital integrated circuits,integrated circuit noise,integrated circuit reliability,low-power electronics,1/f noise,BEOL scheme,CMOS technology,RC delay,SRAM cell,bias temperature instability,extreme low k dielectric,gate dielectric breakdown,hierarchical back-end-of-line scheme,high speed digital transistors,high-k dielectric,hot carrier injection,low power applications,matching factor improvement,reliability,ring oscillator,size 32 nm,static noise margin,temperature 125 degC

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