Study Of Integration Issues Of Ti Salicide Process With Preamorphization For Sub-0.18 Mu M Gate Length Cmos Technologies

A study of integration issues of Ti SALICIDE with preamorphization for sub-0.18 mu m gate length 1.8V CMOS technologies is presented, studying process window and process optimization in terms of the most relevant device parameters and device performance. The process space explored included As pre-amorphization implant (PAI) energy, Ti thickness, silicide rapid thermal processing (RTP) formation temperature and time, silicide RTP anneal temperature and time, and two post-SALICIDE flows: low temperature (T < 500 degrees C except RTP steps) and high temperature (T up to 700 degrees C). An optimized process was obtained with a similar to 45 mn thin silicide, using shallow preamorphization, short anneal time, optimized RTP, and low temperature post-SALICIDE processing, obtaining optimal silicide to source/drain contact resistance (R-C), source and drain series resistance (R-SD), and drive current (I-DRIVE), With low 0.16 mu m gate sheet resistance, low diode leakage and no gate to S/D bridging.