A Robust Embedded Ladder-Oxide/cu Multilevel Interconnect Technology for 0.13 /spl Mu/m CMOS Generation

N Oda,S Ito,T Takewaki,H Kunishima, N Hironaga,I Honma,H Namba,S Yokogawa,T Goto,T Usami,K Ohto,A Kubo,H Aoki,M Suzuki, Y Yamamoto,S Watanabe, T Takeda, K Yamada, M Kosaka,T Horiuchi

2002 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS（2002）

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Key words

CMOS integrated circuits,VLSI,copper,dielectric thin films,electric breakdown,electromigration,integrated circuit interconnections,integrated circuit metallisation,integrated circuit reliability,internal stresses,permittivity,thermal stresses,0.13 micron,0.34 micron,CMOS generation,Cu,Cu interconnect TDDB,Cu metallization,SiO/sub 2/ IMD,dual damascene Cu-plug structure,electromigration test,minimum wiring pitch,packaging flexibility,pressure cooker test,reliability test,robust embedded ladder-oxide/Cu multilevel interconnect technology,single damascene Cu-plug structure,stable ladder-oxide IMD,thermal design flexibility,via stress-migration lifetime,wiring capacitance

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