Direct Cu Plating of High Aspect Ratio Through Silicon Vias (tsvs) with Ru Seed on 300 Mm Wafer
2014 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE / ADVANCED METALLIZATION CONFERENCE (IITC/AMC)（2014）
关键词
copper,electric breakdown,electroplating,integrated circuit reliability,integrated circuit testing,ruthenium,three-dimensional integrated circuits,Atotech TSV III chemistry,Cu,Ru,TSV,bottom-up growth,full wafer direct plating,high aspect ratio through silicon vias,in-line electrical test,physical vapor deposition,plating nonuniformity improvement,sidewall suppression,size 300 mm,structured wafer,void free fill,voltage ramp dielectric breakdown reliability testing
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