An Optimized Architecture for Modulo (2n − 2p + 1) Multipliers

In this express, an optimized architecture for modulo (2(n) - 2(p) + 1) multipliers on the condition n >= 2p is proposed. Compared with the state-of-art, synthesized results demonstrate that the proposed multipliers can achieve an average delay savings of about 7.5% with an average area savings of about 1.4%.