Hierarchical Distribution Network for Low Skew and High Variation-Tolerant Bufferless Resonant Clocking
JOURNAL OF SEMICONDUCTORS(2011)
摘要
We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures. The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process. The post-simulation results show that the hierarchical architecture reduces more than 75% and 65% of clock skew compared with pure mesh and pure H-tree networks, respectively. The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations, which is no more than 1% of the clock cycle of about 760 ps.
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关键词
resonant clock,clock distribution network,clock skew,PVT variation
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