Noise analysis of NPN SOI bipolar transistors for the design of charge measuring systems

This paper is concerned with the analysis of the noise properties of NPN junction bipolar transistors fabricated in a monolithic technology. Such devices are part of a BiCMOS silicon on insulator process, whose suitability for radiation hard applications is being evaluated. A thorough noise characterization, including series and parallel contribution measurements, was performed in view of the design of high speed analog frontend electronics for radiation detectors. For this purpose, a method for optimizing the noise performances of charge measuring systems has been applied to the experimental data from single device characterization.