STATUS OF LUMICAL READOUT ELECTRONICS

The design and measurements of the prototypes of readout electronics for the lumi- nosity detector (LumiCal) at the ILC, developed within the EUDET consortium, are presented. The proposed front-end (FE) architecture comprising switched- gain preamplifier, pole-zero cancellation circuit (PZC) and switched-gain shaper is described. The preamplifier works for a wide range of input capacitance values up to 100 pF. The input charge dynamic range is 0.4 fC to 10 pC and covers more than 4 orders of magnitude. The circuit has to be fast with a peaking time of about 70 ns. The prototype ASICs are designed and fabricated in 0.35 µm CMOS tech- nology. The results of measurements on gain, noise, high input rate performance and crosstalk are presented. In parallel to the FE ASIC the digitizer ASIC (ADC) is also developed and the prototypes are fabricated in 0.35 µm CMOS technology. The design of the pipeline 10 bit ADC with 1.5-stage architecture is described. The functional ADC unit works up to about 35 MHz sampling frequency. Wide spectrum of measurements of static (INL, DNL) and dynamic (SNHR, SINAD, THD) parameters are presented.