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Efficient Per-Flow Queueing in DRAM at OC-192 Line Rate Using Out-of-order Execution Techniques.

2001 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-10, CONFERENCE RECORD(2001)

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DRAM chips,buffer storage,hardware description languages,queueing theory,telecommunication network management,telecommunication network routing,telecommunication switching,10 Gbit/s,OC-192 line rate,QoS,Rambus DRAM,behavioral Verilog,clock-cycle accuracy level,datapath chip,dynamic RAM,efficient chip partitioning,efficient per-flow queueing,flip-flops,hardware description language,large buffer space,line cards,on-chip SRAM,out-of-order execution techniques,quality of service,queue manager,routers,supercomputers,switches
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