A 0.1-to-1.5ghz 4.2mw All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology
IEEE International Solid-State Circuits Conference（2008）
关键词
CMOS integrated circuits,DRAM chips,clocks,delay lock loops,CMOS technology,DRAM chips,all-digital DLL,clock receiver,digital controlled duty-cycle-error detector,duty-cycle correction circuit,frequency 0.1 GHz to 1.5 GHz,power 4.2 mW,size 66 nm,update gear circuit
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