ANALYSIS AND DESIGN OF AN INTEGRATED INTERFACE FOR LEAKY CAPACITIVE SENSORS WITH EMPHASIS ON HUMIDITY SENSORS

This paper presents the analysis and design of an integrated interface for leaky capacitive sensors. For such an application, we developed a novel type of interface circuit. With this circuit it is possible to measure the capacitance of a humidity sensor, at the presence of shunting resistors, with sufficient accuracy. For the signal processing, a relaxation oscillator is used with a modified front-end to optimize the interface circuit for immunity to leakage. Simulation results show, that a 500 kΩ shunt resistance (2µS) causes an error that corresponds to about 0.5% in relative humidity. The interface chip consumes about 1mA and, when implemented in 0.7µm standard CMOS technology, takes a chip area of 2mm2.