Read-disturb and Endurance of SSI-flash E/sup 2/PROM Devices at High Operating Temperatures

The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, V/sub t/: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150/spl deg/C. Finally, bake tests at higher temperatures (250-300/spl deg/C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.