Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch

High-performance and low-power VLIW DSP processors are increasingly being deployed in mobile devices to process video and multimedia applications. The diverse applications of such systems has led to recent research efforts focusing on their resource management and kernel scheduling. In this paper, we address the enhancing the performance of the microkernel for a VLIW DSP processor, called PAC architectures. In order to reduce the number of read and write ports in register files of VLIW architectures, so as to reduce both the power consumption and implementation costs, a distributed register file and multibank register architectures are being adopted in PAC architectures. These methods present challenges for microkernel designs in terms of reducing context switch overhead. In our work, we propose a multiset descriptor mechanism with compiler support to reduce the context switch overheads associated with the use of registers. The experiments were done with the microkernel system called pCore which has an efficient and tiny design that prunes its code size down under 11 Kbytes. Experimental results show that our multiset context-switching mechanism may reduce the context switch overhead up to 30%.