Tightly Integrate Dynamic Verification with Formal Verification: a GSTE Based Approach
Proceedings of the ASP-DAC 2005 Asia and South Pacific Design Automation Conference, 2005（2005）
Key words
formal verification,integrated circuit design,logic design,Intel designs,dynamic checker,formal checker,formal verification,generalized symbolic trajectory evaluation,intermediate monitor circuit,microprocessor design verification,scalar simulation trace,state elements
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined