On reducing peak current and power during test
IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW FRONTIERS IN VLSI DESIGN（2005）
摘要
This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
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关键词
progressive match,progressive match filling,integrated circuit testing,fault simulation,initialization vector,power dissipation,large iscas,power dissipation reduction,hardware modification,low-power electronics,automatic test pattern generation,hamming distance,boundary scan testing,delays,broadside delay fault testing,peak current reduction,circuit cad,peak current,integrated circuit design,resulting launch vector,isc as 89 circuits,pattern tests,fast capture cycle,propagation delay,fault detection,voltage,low power electronics,hardware
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