Youngil Lim

Youngil Lim received the B.S. and M.S. degrees in electrical and electronic engineering from Chungbuk National University, Cheongju, South Korea, in 2005 and 2007, respectively. In 2007, he joined Samsung Electronics, Hwaseong, South Korea, where he was involved in the design and failure analysis of DDR3, LPDDR3, LPDDR4, and LPDDR5 with the Memory Design Team, and has been working as a Principal Engineer since 2020. His current research interests include low-power, high-density, and high-speed DRAM.