Kerem Akarvardar - Department of Electrical Engineering and Center for Integrated Systems;S tanford University;Department of Electrical Engineering and Center for Integrated Systems, S tanford University

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个人简介

Kerem Akarvardar (Senior Member, IEEE) received the Ph.D. degree in electrical engineering from Grenoble Institute of Technology, Saint-Martin-d’Hères, France. He is a Senior Program Manager with TSMC Corporate Research, San Jose, CA, USA. He focuses on technologies to support AI hardware and their co-optimization with design, architecture, and algorithms. Prior to TSMC, he was with GlobalFoundries as an Assignee to IBM Semiconductor at Albany Nanotech, Albany, NY, USA.

研究兴趣

论文共 107 篇作者统计合作学者相似作者

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34.4 A 3nm, 32.5TOPS/W, 55.0tops/mm2 and 3.78mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

Haruhiko Fujiwara,Hatsumi Mori, Wei-Chang Zhao, Kinshuk Khare, Cheng-En Lee,Xiaochen Peng, Vishal Joshi, Chao-Kai Chuang, S.-C. Hsu, Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien, Yao-Yi Liu, Y. S. Lai, Chia-Fu Lee, Tan‐Li Chou,K. Akarvardar, Saman Adham, Yih Wang, Yu-Der Chih, Yen-Huei Chen,Haijun Liao, Tsung-Yung Jonathan Chang

openalex（2024）

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34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm² and 3.78Mb/mm² Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

Hidehiro Fujiwara,Haruki Mori,Wei-Chang Zhao, Kinshuk Khare,Cheng-En Lee,Xiaochen Peng, Vineet Joshi,Chao-Kai Chuang, Shu-Huan Hsu,Takeshi Hashizume, Toshiaki Naganuma, Chen-Hung Tien,Yao-Yi Liu, Yen-Chien Lai,Chia-Fu Lee,Tan-Li Chou,Kerem Akarvardar,Saman Adham,Yih Wang,Yu-Der Chih,Yen-Huei Chen,Hung-Jen Liao,Tsung-Yung Jonathan Chang

2024 IEEE International Solid-State Circuits Conference (ISSCC)（2024）

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34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm 2 and 3.78Mb/mm 2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

IEEE International Solid-State Circuits Conferencepp.572-574, (2024)

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Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework

Xiaoyu Sun,Xiaochen Peng, Sai Zhang,Jorge Gomez,Win-San Khwa, Syed Sarwar,Ziyun Li, Weidong Cao, Zhao Wang,Chiao Liu,Meng-Fan Chang, Barbara Salvo,Kerem Akarvardar,H.-S. Philip Wong

ACM Transactions on Design Automation of Electronic Systems (2024)

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Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros

Xiaoyu Sun, Weidong Cao,Brian Crafton,Kerem Akarvardar,Haruki Mori,Hidehiro Fujiwara, Hiroki Noguchi,Yu-Der Chih,Meng-Fan Chang,Yih Wang,Tsung-Yung Jonathan Chang

IEEE transactions on computer-aided design of integrated circuits and systemsno. 4 (2024): 1191-1205

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Technology Prospects for Data-Intensive Computing

Kerem Akarvardar,H-S Philip Wong

Proceedings of the IEEE（2023）

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A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update

Haruki Mori,Wei-Chang Zhao,Cheng-En Lee,Chia-Fu Lee,Yu-Hao Hsu,Chao-Kai Chuang,Takeshi Hashizume, Hao-Chun Tung,Yao-Yi Liu,Shin-Rung Wu,Kerem Akarvardar,Tan-Li Chou,Hidehiro Fujiwara,Yih Wang,Yu-Der Chih,Yen-Huei Chen,Hung-Jen Liao,Tsung-Yung Jonathan Chang

ISSCCpp.132-133, (2023)

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An 89TOPS/W and 16.3TOPS/mm

user-5aceb7ef530c7001b97ba534（2021）

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MLC PCM Techniques to Improve Nerual Network Inference Retention Time by 105X and Reduce Accuracy Degradation by 10.8X

W. S. Khwa,K. Akarvardar,Y. S. Chen,Y. C. Chiu, J. C. Liu, J. J. Wu, H. Y. Lee, S. M. Yu, C. H. Lee, T. C. Chen, Y. C. Lin, C. F. Hsu, T. Y. Lee, T. K. Ku, C. H. Kuo, J. Y. Wu, X. Y. Bao, C. S. Chang, Y. D. Chih, H.-S. P. Wong, M. F. Chang

Symposium on VLSI Technologypp.1-2, (2021)

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