Ji-Yeon Shin

Ji-Yeon Shin received the B.S. degree in electronics engineering from the Sungkyunkwan University, Suwon, South Korea, in 2009. She joined the Semiconductor Memory Division, Samsung Electronics, Hwaseong, South Korea, in 2009. From 2009 to 2018, she was with Flash Design Team, where she designed high-speed IO of NAND and F-chip. Since 2018, she has been involved on NAND Product Planning Team. She worked for Business Engagement and now plans specification of the next-generation NAND Flash memory.