J. P. Soulie - Imec | 人才画像

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论文共 10 篇作者统计合作学者相似作者

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Monolithic Complementary Field Effect Transistors (CFET) Demonstrated Using Middle Dielectric Isolation and Stacked Contacts

Steven Demuynck,Victor Vega-Gonzalez,C. Toledo de Carvalho Cavalcante,L. Petersen Barbosa Lima, K. Stiers, C. Sheng,A. Vandooren,M. Hosseini, X. Zhou,Hans Mertens,Thomas Chiarella,Jürgen Bömmels,Roger Loo,E. Rosseel,Clement Porret, Y. Shimura, A. Akula,G. Mannaert,S. Choudhury,V. Brissonneau,E. Dupuy, T. Sarkar,Nathali Franchina-Vergel,A. Peter,Nicolas Jourdan,J. P. Soulie,Kevin Vandersmissen,F. Sebaai,P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar,K. D'Have,B. T. Chan, A. Sepulveda Marquez,R. Langer, I. Gyo Koo,E. Altamirano Sanchez,Katia Devriendt, P. Rincon Delgadillo,F. Lazzarino,Jérôme Mitard,J. Geypen,E. Grieten,D. Batuk, Y.-F. Chen, F. Verbeek,F. Holsteyns,S. Subramanian,N. Horiguchi,S. Biesemans

Symposium on VLSI Technologypp.1-2, (2024)

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Directional Etching of Barrierless NiAl Lines on 300mm Wafers for Interconnects Applications

S. Kundu,J.-P. Soulié,G. Marti, F. U. Okudur,L. Souriau,F. Lazzarino,G. Murdoch,S. Park,Z. Tőkei

IEEE Electron Device Lettersno. 99 (2024): 1-1

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Front-side Integration of Middle-of-line Stacked Contacts for Monolithic CFET

V. Vega-Gonzalez, K. Stiers, C. Sheng,S. Demuynck,C Toledo de Carvalho Cavalcante, L. Petersen,T. Chiarella,J. Boemmels, T. Sarkar, N. Franchina Vergel,D. Radisic,R. Loo,E. Rosseel,C. Porret,G. Mannaert,S. Choudhury,V. Brissonneau,E. Dupuy,A. Peter,N. Jourdan,J-P. Soulié,T. Hakamata, A. Romo-Negreira, R. Clark,K. Vandersmissen,F. Sebaai,P. Puttarame Gowda, J.G. Lai, A. Mingardi, S. Kumar Sarkar,B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo,E. Altamirano Sanchez,K. Devriendt, P. Rincon Delgadillo,F. Lazzarino,J. Mitard,J. Geypen,D. Batuk, Y-F. Chen, F. Verbeeck,F. Holsteyns,S. Subramanian,Zs. Tőkei,N. Horiguchi,S. Biesemans

2024 IEEE International Interconnect Technology Conference (IITC)pp.1-3, (2024)

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Epitaxial Growth of Magnetron Sputtered NiAl on Ge Mediated by Native GeOx

M. Ben Chroud,M. Korytov,J-p Soulie,C. Adelmann,J. Swerts, K. Temst,R. Carpenter

JOURNAL OF PHYSICS D-APPLIED PHYSICSno. 13 (2024)

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Integration of a Stacked Contact MOL for Monolithic CFET

Victor Vega-Gonzalez,D. Radisic,Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster,Y. Oniki, P. Puttarame,Kevin Vandersmissen,J. P. Soulie,A. Peter,A. Sepulveda,D. Batuk,G. T. Martinez,Olivier Richard,Jürgen Bömmels,S. Biesemans,E. Dentoni Litta,Naoto Horiguchi, S. Park,Zsolt Tokei

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2023)

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Nanosheet-based Complementary Field-Effect Transistors (cfets) at 48nm Gate Pitch, and Middle Dielectric Isolation to Enable CFET Inner Spacer Formation and Multi-Vt Patterning

Hans Mertens,M. Hosseini,Thomas Chiarella,D. Zhou,S. Wang,G. Mannaert,E. Dupuy,D. Radisic,Z. Tao,Y. Oniki,Andriy Hikavyy, R. Rosseel, A. Mingardi,S. Choudhury,P. Puttarame Gowda,F. Sebaai,A. Peter,Kevin Vandersmissen,J. P. Soulie,An De Keersgieter,L. Petersen Barbosa Lima, C. Cavalcante,D. Batuk,G. T. Martinez,J. Geypen,F. Seidel, K. Paulussen,P. Favia,Jürgen Bömmels,Roger Loo, P. Wong, A. Sepulveda Marquez,B. T. Chan,Jérôme Mitard,S. Subramanian,S. Demuynck,E. Dentoni Litta,N. Horiguchi,S. Samavedam,S. Biesemans

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (2023)

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Scaled FinFETs Connected by Using Both Wafer Sides for Routing Via Buried Power Rails

IEEE Transactions on Electron Devicesno. 12 (2022): 7173-7179

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Buried Power Rail Metal Exploration Towards the 1 Nm Node

2021 IEEE International Electron Devices Meeting (IEDM) (2021)

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First Demonstration of Ruthenium and Molybdenum Word Lines Integrated into 40nm Pitch 3D-NAND Memory Devices

A. Ajaykumar,L. Breuil,K. Katcko,F. Schleicher, F. Sebaai,Y. Oniki,S. Ramesh,A. Arreghini,L. Nyns,J. -P. Soulie,J. Stiers,G. Van den Bosch,M. Rosmeulen

Symposium on VLSI Technologypp.1-2, (2021)

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