Hideyuki Kabuo

Hideyuki Kabuo (M'03) received the B.S. and M.S. degrees in computer science from Kumamoto University, Kumamoto, Japan, in 1985 and 1987, respectively. In 1987, he joined Matsushita Electric Industrial Co., Ltd., renamed to Panasonic Corporation in 2008, where he was engaged in developing SPARC RISC microprocessors for EWS, and was leading the development of low-power DSPs for 2G speech CODEC and 3G baseband processing in mobile phone terminals and base stations. Currently, he has responsibility of developing processor core technologies, low-power and high-speed circuits and systems for processor cores and multimedia SoCs. He holds 44 patents, including 31 in the U.S. and 13 in Japan. Mr. Kabuo served as a Technical Program Committee member of the Symposium on VLSI Circuits (2001–2011) and the Asian Solid-State Circuits Conference (2005–2010). He was a Technical Program Chair for the Symposium on VLSI Circuits (2012–2013), and is a symposium co-chair for 2014.