High-precision positioning detection technology for large-size fan-out panel-level package chips

During the process of large-scale plastic sealing of board-level packages, significant deformations can occur due to differences in thermal expansion coefficients between the carrier board, adhesive film, and sealing layer after cooling. These deformations can cause deviations in the positions of the chips from the ideal design drawings, which can affect the quality of the subsequent wiring layer production. To address this issue, a chip offset detection method has been proposed that combines a motion platform and an industrial camera to visually inspect chips on the carrier board and calculate offset data to improve the quality of subsequent wiring layer production. The method involves measuring the positioning error of the motion platform and establishing a geometric error model for error compensation. An improved Edge Drawing algorithm is used to extract pixel-level edges from the chip image, and sub-pixel edge detection based on Zernike moments is used to improve edge detection accuracy. Using the least squares method to fit the edge of the chip, a carrier board coordinate system is established based on reference points, and the angular deviation between the chip coordinates and the carrier board coordinate system is solved using the homogeneous transformation matrix. This proposed chip position detection system is of great significance and can effectively solve the problem of chip position deviation in large-scale panel-level packaging. Experimental results demonstrate that the motion platform error compensation model can effectively reduce platform motion errors, and the chip position repeat positioning accuracy reaches 0.06mm, meeting industrial requirements.