A 521pW, 0.016%/V Line Sensitivity Self-Biased CMOS Voltage Reference With DIBL Effect Compensation Using Adaptive VGS Control

This paper proposes an ultra-low-power self-biased CMOS voltage reference (SBCVR) with the drain-inducedbarrier-lowering (DIBL) effect compensation to improve the line sensitivity (LS) and low-frequency power supply rejection ratio (PSRR). To reduce the dependence of bias current (IB) on the supply voltage (VDD) owing to the DIBL effect, the gate-source voltage (VGS) of biasing transistor is adaptively regulated by VDD. In this way, the DIBL effect compensation is achieved, while the IB is almost immune to VDD. The presented SBCVR is fabricated in a 0.18-lm CMOS process, while 18 samples have been measured. The results show that its average LS reaches 0.016%/V and has been decreased by almost 85% compared to the one without the DIBL effect compensation. The design can also achieve a PSRR of -62.5dB at 10Hz. Meanwhile, the average reference voltage (VREF) is 317.6mV with a variation of 0.52% σ/μ. The average temperature coefficient (TC) is 86.6 ppm/∘C without trimming from 0∘C to 100∘C, and the minimum power consumption at 27∘C is 521pW. The area of the reported SBCVR with the DIBL effect compensation is only 0.0016mm2.