Design optimization of a Dual-Interlocked-Cell in 65 nm CMOS tolerant to Single Event Upsets

Dual-Interlocked-Cell (DICE) latches are tolerant to Single Event Effects (SEE) by design owing to intrinsic redundancy. In nanometric technologies, as in the 65 nm scale, there are new SEE vulnerabilities associated with charge sharing between nodes. Herein we present a systematic analysis of the robustness against radiation using a simulation software tool for analog and mixed-signal circuits (AFTU) that emulates the possible effects generated by particle impacts. In this paper, we evaluate the influence of SEE on circuit performance using this tool as an RHbD assessment for designers. An exhaustive study of the possible vulnerabilities of the DICE architecture is performed, including an evaluation of the proximity between critical nodes at the layout level. As a result, we propose several modifications to the cell implementation to optimize its robustness against Single Event Upsets (SEU). An assortment of five designs with different variations of the original DICE scheme was sent for fabrication on a new chip and tested under ion beams, with promising results showing a clear improvement in the SEU sensitivity of the cell. The best results come from a redesign of the load circuitry to avoid a SET2SEU effect and full interleaved layout to avoid charge sharing effects after a single event.