Low Power Decoder Architecture of Product Code for Storage Controller

Error correction codes (ECCs) are essential for correcting the errors caused by the physical characteristics of 3D NAND flash in flash solution products. In this paper, we introduce low power decoder architecture for product code. Precisely, by using Hamming product code and Chase-Pyndiah algorithm, this work takes not only the same correction capability and area as low-density parity-check decoder, but also less power with relatively simple operation for decoding. Only the log likelihood ratios of error-suspicious bits are gathered in SRAM for the next iteration of decoding, so that the power consumption and area of SRAM read/write decrease. Compared with the conventional ECC decoder with the same correction capability and area, our decoder has achieved an average power reduction of 22.4%.