A Strategy to Mitigate Single Event Upset in 14 nm CMOS Bulk FinFET Technology

Abstract 3D TCAD simulations demonstrated that reducing the distance between the well boundary and NMOS or PMOS can mitigate the cross section of Single Event Upset (SEU) in 14 nm CMOS bulk FinFET technology. The competition of charge collection between well boundary and sensitive nodes, the enhanced restore currents and the change of bipolar effect are responsible for the decrease of SEU cross section. Different from Dual-interlock cells (DICE) design, under the presence of enough taps to ensure the rapid recovery of well potential, this approach is more effective under heavy ion irradiation of higher LET. Besides, the feasibility of this method and its effectiveness with feature size scaling down are discussed.