3D TSV Interposer Technology with Cu/SnAg Microbump Interconnections

Microelectronics packaging is driven by the continuous increase in demands for smaller, faster, and cheaper products with enhanced performances. Flip-chip technology and multichip packaging are developed to meet the market needs. In recent years, the concept of multichip packaging is evolved into system-in-a-package (SIP). Major advantages of SiP are that different types and generations of devices are assembled in a single package, providing high flexibility for systems designers. One way of integrating more devices into a smaller volume is 3-D packaging techniques by stacking the chips vertically. The 3-D packaging can be broadly classified as chip stacking and package stacking. In chip stacking technology, dice are stacked. This technology has advantages of increased die combination and flexibility. These days there is more and more needs for 3D TSV interposers. Based on silicon or glass, 3D TSV interposers are next generation substrate technology which aims at replacing traditional PCB laminate or ceramic technologies for the sake of extreme miniaturization and performance. This intermediate TSV 3D technology is perceived as a bridging or linking platform between today¡¯s 2D and future genuine/ultimate 3D that will start beyond 2013. This paper will highlight some of the recent advancements in 3D TSV interposer design, and fabrication and Cu/SnAg microbumping as well as what is being envisioned and developed to address future technology requirements in 3D TSV packaging. The advantage and applications of TSV silicon interposer technology will be presented with several examples. The process flow of TSV interposer fabrication, microbumping, assembly and packaging challenges, and performance characteristics will be also discussed.