A 112-Gb/s PAM-4 Transmitter with 8: 1 MUX in 28-Nm CMOS.

This paper proposes a 112 Gb/$s$ quarter-rate four-level pulse-amplitude modulation (PAM-4) transmitter (TX) using lUI pulse generation based 8:1 multiplexer (MUX) which is adequate for high-speed operation. The transmitter includes current-mode logic (CML) driver, quadrature clock generator and phase interpolator (PI) for clock generation and tap generation for 3-tap feed-forward equalizer (FFE). The key feature of 8:1 MUX is combining MSB/LSB path with 4:1 serializing to reduce the area and power consumption. The chip is implemented in 28-nm CMOS technology and core block occupies an area of 0.202 mm2. The simulated power efficiency of proposed MUX is 0.21 pJ/b.