Process Variation Tolerant Wide-Band Fast PLL with Reduced Phase Noise Using Adaptive Duty Cycle Control Strategy

This paper presents the effects of manufacturing process variations on the phase-locked loop (PLL) performances like lock time, lock range and phase noise. At higher operating frequencies, due to process variations, there is a shift in the duty cycle of the divider output to phase-frequency detector, which leads to lock failure. To alleviate this problem an adaptive duty cycle control (ADCC) strategy is proposed and used in the frequency divider present in the feedback path of PLL. The proposed technique makes the PLL process variation tolerant and lock at higher frequencies where otherwise PLL was out of lock. It assists the PLL to lock faster and achieve low phase noise at all frequencies under nominal conditions. The operating temperature range is also enhanced to -50 degrees to 50(o) C. Simulation studies in Cadence design environment on a 3.5 GHz PLL reveals the lock range improvement of 40% and phase noise improvement of 15%.