Suppressing Gate Voltage Oscillation in Paralleled SiC MOSFETs for HEV/EV Traction Inverter Application

This paper investigates the gate voltage (V-gs) oscillation of paralleled SiC MOSFETs during fast switching transient. Based on the study, the paper proposes to add the coupled inductance and/or the additional path on Kelvin source of paralleled MOSFETs to suppress the amplitude of gate voltage oscillation. The paper considers 1-in-1 and 2-in-1 power modules, and devices with on-chip current sense, which are used in many HEV/EV (Hybrid Electric Vehicle/Electric Vehicle) traction inverters. Since the proposed methods only require the modifications on the low power signal circuit instead of the high power circuit, they are easy to be implemented with small volume and weight, low power consumption, and low cost, which are required by automotive application.