A Low-Power 12-Bit 2gs/S Time-Interleaved Pipelined-Sar Adc In 28nm Cmos Process

This paper presents a low-power 2-channel 12-bit 2GS/ s time-interleaved pipelined-SAR ADC in 280m CMOS process. The design adopts SHA-less front-end, capacitor sharing between stages, current-reused and ping-pong operated MDAC amplifier, and hybrid reference buffer to reduce power consumption and optimize performance. Pre-layout simulation with noise shows that the proposed ADC achieves SNDR and SFDR of 64.1dB and 69. SdB respectively at Nyquist frequency. The effective resolution bandwidth is extended to 3.2GHz. The ADC consumes only SOmW, in which 30mW is dissipated by the wideband input buffer. At Nyquist frequency, the proposed ADC achieves a Walden FOM of 19fJ/conv.-step.