A Low-Power 12-Bit 2gs/S Time-Interleaved Pipelined-Sar Adc In 28nm Cmos Process
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)（2018）
关键词
CMOS process,low-power 2-channel SAR ADC,SHA-less front-end,Nyquist frequency,wide-band input buffer,Waiden FOM,hybrid reference buffer,time-interleaved pipelined-SAR ADC,power consumption,ping-pong operated MDAC amplifier,power 50.0 mW,power 30.0 mW,size 28.0 nm,bandwidth 3.2 GHz
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