Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

Kevin J Fischer,M Agostinelli,Cerisse E Allen, D Bahr,M Bost,P Charvat,Vinay B Chikarmane,Qiang Fu, C S Ganpule,M Haran, M Heckscher,H Hiramatsu, Eungsoo Hwang,P S Jain,I Jin,R Kasim, S Kosaraju,Keu Sung Lee, Haidong Liu, Ryan Mcfadden,S K Nigam, Rishi Patel,C Pelto,P Plekhanov, M B Prince,C Puls, Sathish Rajamani,D Rao,Paul B Reese, A Rosenbaum, S Sivakumar, Byounga Song, M Uncuer, Simon C Williams, Minmin Yang,P Yashar,S Natarajan

2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)（2015）

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Abstract

We describe here Intel's 14nm high-performance logic technology interconnects and back end stack featuring 13 metal layers and a tri-metal laminated metal-insulator-metal (MIM) capacitor. For the first time on a logic product in high volume, multiple layers (M4 and M6) incorporate an air gap integration scheme to deliver up to 17% RC benefit. Pitch Division patterning is introduced to deliver high yield capable interconnect layers with a minimum pitch of 52nm.

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Key words

low-k interconnect stack,multilayer air gap,trimetal-insulator-metal capacitors,high volume manufacturing,high performance logic technology interconnects,back end stack,trimetal laminated metal-insulator-metal capacitor,MIM capacitor,size 14 nm

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