Layout optimizations to decrease internal power and area in digital CMOS standard cells

This paper presents several layout optimizations in order to decrease both, the internal power and the area of digital standard cells. A new D flip-flop (Dff) is designed using advanced design rules and lower active widths. Post-layout simulations are performed and the internal power of a new Dff is reduced by 20% while clock-to-Q delay remains unchanged. Indeed, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. The saturation current (IDSAT) is improved by 15% and 50% for NMOS and PMOS transistors, respectively. Moreover, the area of the new Dff is reduced by 20% by using lower active widths and new optimized design rules.