Digital Statistical Analysis Using VHDL: Impact of Variations on Timing and Power Using Gate-Level Monte Carlo Simulation

Variations of process parameters have an important impact on reliability and yield in deep sub micron IC technologies. One methodology to estimate the influence of these effects on power and delay times at chip level is Monte Carlo Simulation, which can be very accurate but time consuming if applied to transistor-level models. We present an alternative approach, namely a statistical gate-level simulation flow, based on parameter sensitivities and a generated VHDL cell model. This solution provides a good speed/accuracy tradeoff by using the event-driven digital simulation domain together with an extended consideration of signal slope times directly in the cell model. The designer gets a fast and accurate overview about the statistical behavior of power consumption and timing of the circuit depending on the manufacturing variations. The paper shortly illustrates the general flow from cell characterization to the model structure and presents first simulation results.