A Self-Calibrated Voltage Scaling Technique for Reliable Interconnections in Network-on-Chip

Network-on-Chip (NoC) architectures are considered against variations of interconnections in this paper. A self-calibrated voltage scaling technique is proposed to provide reliable and low energy interconnections in network- on-chip. The self-calibrated voltage scaling technique adjusts the operation voltage by two stages, which are crosstalk-aware test error detection stage and run-time error detection stage. The crosstalk-aware test error detection stage detects the error by maximal aggressor fault (MAF) test patterns in the testing mode. The run-time error detection stage detects errors by double sampling data checking technique; moreover, it provides the tolerance to timing variations. According to the error detections, the self-calibrated voltage scaling technique can reduce the voltage swing for energy reduction and guarantee the reliability at the same time. The energy of link wires at the lowest voltage can achieve nearly 64.47% reduction compared to un-coded link wires.