Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

Thermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating (SH) effects and thermal propagation in fully depleted silicon-on-insulator (FD-SOI) technology, measured from room temperature (300 K) down to 4.2 K, using the gate resistance thermometry technique. The channel temperature increase and the in-plane temperature profile were investigated and analytically modeled, together with the thermal coupling between simultaneously operating devices. We demonstrated a major constraint for extremely low-temperature operation due to abrupt channel temperature rise even at sub-1 mW input power, which propagates over hundreds of nanometers along the Si layer. Thermal coupling was identified as a source for SH aggravation, and needs to be particularly optimized to limit the heating of cryo-circuits.