Systematic Study of the Incorporation of Quantum-Coupling 2-D Materials in the FET Gate/Channel Stack for Steep Subthreshold Slope

IEEE TRANSACTIONS ON ELECTRON DEVICES(2024)

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摘要
An alternative way to overcome the Boltzmann "tyranny" limit of the MOSFET subthreshold slope (SS) (60 mV/decade at room temperature) is to employ quantum coupling materials in the channel/gate-stack, in search of fast switching nanoscale devices. In this article, we explore the incorporation of a range of 2-D quantum materials in the FET gate/channel stack and find suitable combinations, which break the sub-60-mV/dec Boltzmann limit of minimum SS. We investigate the incorporation of layers of these materials in both the gate-stack and the channel, and their precise location and thickness, in order to find the parameter window of these quantum coupled devices for a steep SS. We also analyze the influence of channel strain and the doping of the "inserted" layer on the SS. We will present a brief overview based on our results of the different parameters that must be considered when designing the steep SS transistor, using the channel-gate-stack coupling concept.
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关键词
Logic gates,Voltage,Quantum capacitance,Electrons,Electric potential,Correlation,Strain,Channel strain and doping,density functional theory (DFT) simulation,low density of state (DOS),negative quantum capacitance (NQC),quantum coupling,quantum materials,steep subthreshold slope (SS) FET
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