On-Chip Write & Verify and Endurance Enhancer Circuits towards Multi-level RRAM Array

In-memory computing based on multi-level RRAMs has shown great potential in neural network computations. In-situ training is becoming increasingly attractive, but requires accurate on-chip RRAM cell write. In this paper, we demonstrate a fully on-chip write and verify circuit and a novel methodology to improve the endurance of RRAM. Simulations show up to $120 \times$ programming speed improvement, achieving 86% reduction of conductance standard deviation and $50 \times$ longer device lifetime.