A Ka-band 27.6-dBm power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology

This paper presents a Ka-band power amplifier with a compression-state large-signal matching approach in 130-nm CMOS SOI technology. The amplifier employs a quad-branch topology based on zero-degree power combiners/splitters, with each branch comprising two differential stages, each containing four stacked FETs. With a compression-state large-signal matching approach, this design achieves the saturated output power (Psat) of 27.6 dBm with 14.1 % peak power added efficiency (PAE), output 1-dB compression point (OP1dB) of 20.1 dBm at 35 GHz, according to electromagnetic simulation (EM) results. Additionally, it exhibits a peak gain of 39.2 dB at 33 GHz and a 3-dB bandwidth across 32–38 GHz. Offering a low-cost solution suitable for phased array radars and satellite communications.