Parallel AIG Refactoring via Conflict Breaking
arxiv(2024)
摘要
Algorithm parallelization to leverage multi-core platforms for improving the
efficiency of Electronic Design Automation (EDA) tools plays a significant role
in enhancing the scalability of Integrated Circuit (IC) designs. Logic
optimization is a key process in the EDA design flow to reduce the area and
depth of the circuit graph by finding logically equivalent graphs for
substitution, which is typically time-consuming. To address these challenges,
in this paper, we first analyze two types of conflicts that need to be handled
in the parallelization framework of refactoring And-Inverter Graph (AIG). We
then present a fine-grained parallel AIG refactoring method, which strikes a
balance between the degree of parallelism and the conflicts encountered during
the refactoring operations. Experiment results show that our parallel refactor
is 28x averagely faster than the sequential algorithm on large benchmark tests
with 64 physical CPU cores, and has comparable optimization quality.
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