RESET Kinetics of 28 nm Integrated ReRAM

Redox-based resistive switching random access memory (ReRAM) which is frequently discussed as a promising non-volatile memory as well as a central element in novel neuromorphic computing applications, is typically integrated in 1-transistor-1-resistor (1T1R) structures. While the access transistor is required as a selective device and acts as an effective current compliance during SET, it may hinder the RESET operation due to its series resistance. As demonstrated in our previous study, this may lead to a rare endurance failure. In this paper, we investigate the impact of the access transistor on the RESET kinetics in 100k BEOL integrated ReRAM cells, accompanied by 1D Kinetic Monte Carlo simulations. It is demonstrated that the RESET speed is affected by the voltage divider of transistor and ReRAM cell, where the initial cell resistance, the gate voltage and the transistor geometry (i.e., width over length ratio w/L) are crucial. Further, it is demonstrated that the operation point of the 1T1R voltage divider can be shifted between the linear and the saturation regime of the transistor transfer characteristics.