14.6 A 10A Computational Digital LDO Achieving 263A/mm² Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

In mobile SoC applications, the power rails of multicore CPUs have been merged by CPU cluster to simplify the PMIC-SoC power rails in limited PCB area (VDD LIT , VDD MID and VDD BIG in Fig. 14.6.1). In order to optimize the power of each CPU core, integrated LDOs (iLDO) have recently been proposed [1–4]. However, the cost is quite high to allocate additional power-FETs and power routing, which occupy a large area in the SoC. Therefore, reducing power-FET-area is key to integrate LDOs in a mobile SoC. A previously reported LDO [1] reduced area by using bypass mode power-FETs to supply a portion of load current. However, the load current was still supplied by an analog LDO, which requires significant area. The digital LDO (DLDO) proposed in [2] needs additional power-FETs and the current delivery path could show voltage gradients from the power-FET area to the middle of the core logic area. The maximum clock frequency of a CPU core is over 3GHz in a mobile SoC and the load current slope can reach over 1A/ns in worst case. Thus, ultra-fast transient response is necessary for a DLDO. The DLDO in [2] has a local loop to achieve fast transient response, but the local loop includes an analog current comparator which increases design complexity. [3] and [4] use a dedicated threshold voltage to detect undershoot or overshoot voltage and increase the clock speed or gain of the controller. For fast transient response, the threshold voltage should be close to the target voltage, but if the threshold voltage window is too small, unstable operation may occur, such as limit cycle oscillation (LCO).